Epitaxy refers to the growth by deposition of a single crystal film on top of a crystalline substrate. Epitaxial layers are used in a variety of semiconductor devices such as Insulated Gate Bipolar Transistors (IGBTs). Epitaxially grown layers are desirable for these types of devices due to having a relatively low defect density and because they can be doped independently of an underlying substrate.
Chemical vapor deposition (CVD) is a process that is used to form epitaxial layers. With CVD, a wafer substrate is exposed to gaseous precursors at high temperatures to produce the epitaxial layer. The surface of the wafer substrate acts as a seed crystal and the epitaxial layer takes on the crystalline lattice structure and lattice orientation of the surface of the substrate.
The CVD process can lead to the formation of undesired structural imperfections within the crystalline lattice structure of the wafer substrate and/or the epitaxial layer during growth. These structural imperfections typically include point defects (vacancies), line defects such as slip lines (dislocations), and planar defects (stacking faults). Slip lines and stacking faults are dislocations caused by a local shift of atomic planes within the wafer's lattice structure and can propagate through the wafer for significant distances. Usually slip lines start at an edge of the wafer and begin with a shift of the outermost atomic planes at the edge of the wafer. Slip lines and stacking faults can permanently degrade the electrical and physical characteristics of a wafer and can cause significant leakage currents within devices that are formed on the wafer.
A frequent cause of slip lines and stacking faults are temperature gradients that occur between the center and edge of a wafer when a CVD process is used to form the epitaxial layer. The temperature gradients cause thermal stress within the wafer that is relaxed by formation of dislocations such as slip lines. The majority of slip lines start to be formed within the edge regions of the wafer. A frequent source or starting point for slip line formation are localized defects or mechanical stress that is prevalent in these regions. FIG. 1 illustrates a top plan view of a wafer surface scan result at 100. The wafer has a surface crystallographic plane orientation of {100} with a flat or notch at a bottom edge of the wafer. The surface scan was completed after an epitaxial layer was formed over the wafer. The wafer surface scan result reveals slip line defects 104 that lie along a [011] direction and begin at edge 102 of the wafer. Slip line defects 104 continue in direction 106 until termination. Slip line defects 108 lie along a [001] direction and begin at edge 102 of the wafer. Slip line defects 108 continue in direction 110 until termination. Also, at two other areas having 90° azimuthal angles, slip will occur because of the vertical matching of {111} planes at the wafer edge.
One approach that has been used to limit the formation of slip lines in wafers during a CVD process is to minimize wafer temperature gradients through the use of process controls and process equipment selection. However, due to large temperature gradients and enhanced mechanical stress that occurs within the 300 millimeter (12 inch) wafers that are now being used to manufacture devices such as IGBTs, minimizing slip line formation to acceptable levels is becoming increasingly difficult to achieve.